Career Profile

Minhyuk Kweon is currently Master-Ph.D integrated student in the Department of Electrical Engineering in Pohang University of Science and Technology (POSTECH), Korea. He is working with Professor Seokhyeong Kang in CAD & SoC Design Lab(CSDL).

His reseach interest includes Physical Design in VLSI, especially placement problem in advanced technology node and ML-CAD (Machine Learning Computer Aided Design).

Experiences

Graduated Student Researcher

Feb.2020 - Present
CAD & SoC Design Lab(CSDL) in POSTECH, Prof, Seokhyeong Kang

Visiting Student Researcher

May.2022 - Dec.2022
ABK group in UCSD, Prof, Andrew B. Kahng

Undergraduated Student Researcher

Jan.2019 - Feb.2020
CAD & SoC Design Lab(CSDL) in POSTECH, Prof, Seokhyeong Kang

Intern (Postech SES program)

Jul.2018 - Aug.2018
Samsung Electronics CE/IM Visual Display (VD), LED display team

Projects

Software Systems for AI Semiconductor Design

- IITP, Apr.2021 - Present

Artificial Intelligence (AI) Model for Predicting Display Panel Performance.

- LG Display, Aug.2021 - Jul.2022

Wafer Scale Physics Modeling (ISPD contest 2021)

- Cerebras, Jan.2021 - Mar.2021

Ternary Microprocessor

- IDEC MPW (Samsung 28nm), Sep.2020 - Jul.2021

Scalable Quantum Computer Technology Platform Center

- NRF Engineering Research Center (ERC), Jan.2020 - Feb.2021

Self-Driving Vehicle Routing Algorithm Simulator

- WaveM, Jan.2020 - May.2020

Conferences

  1. GAN-Dummy Fill: Timing-aware Dummy Fill Method using GAN
  2. Myong Kong, Daeyeon Kim, Minhyuk Kweon and Seokhyeong Kang
    The 32nd ACM Great Lakes Symposium on VLSI (GLSVLSI), 2022
  3. A Fast and Scalable Qubit-Mapping Method for Noisy Intermediate-Scale Quantum Computers
  4. Sunghye Park, Minhyuk Kweon, Daeyeon Kim, Jae-Yoon Sim and Seokhyeong Kang
    The 59th ACM/IEEE Design Automation Conference (DAC), 2022

Domestic

  1. 2.5D Interposer Bus Routing for Multi-Flip Chip Designs
  2. Sung-yun Lee, Daeyeon Kim, Minhyuk Kweon and Seokhyeong Kang
    The 27th Korean Conference on Semiconductors (KCS), 2020

Awards

  1. Honorable mention in the ISPD Contest 2020 (Wafer-Scale Deep Learning Accelerator Placement)
  2. 3rd place in the ISPD Contest 2019 (LEF/DEF based Initial Detailed Routing Contest)

Teaching Assistance (TA)

  1. [EECE490F] Introduction to VLSI Design, Spring 2020
  2. [EEB101] Biomedical System Semiconductor Integrated Design Basics, Fall 2020
  3. [MOOC] System Semiconductor Design, Fall 2020 - Winter 2021

Skills

    Linux
    ― Server manager
    Programming Language / Script / Hardware Description Language (HDL)
    ― C/C++, Python, Tcl, Verilog
    Electronic Design Automation (EDA) Tools
    CADENCE
    ― Xcelium (ncverilog & simvision), Innovus
    SYNOPSYS
    ― Hspice, Design Compiler, Lib Compiler, PrimeTime, IC Compiler